Marco Faltelli

PhD Student, University of Rome Tor Vergata

My resume
Rome, Italy
marco.faltelli@uniroma2.it

Research Interests

Fast Packet Processing, High Performance Computing, Hardware-Software Co-design, Data Center Networks, SmartNIC/FPGA offloading

Network Drivers, Operative Systems

Bio

I am a PhD student in Computer Science at the University of Rome Tor Vergata under the supervision of Prof. Giuseppe Bianchi and Prof. Francesco Quaglia. My research activities combine computer networking and computer architecture to design high performing, scalable architectures for both network hardware and software solutions.
My research has been awarded with a Microsoft Research PhD Fellowship.
In the past, I collaborated with CNIT on the 5G-PICTURE European project.
I further collaborate with Axbryd, a startup company founded from the NetProg group of the University of Rome "Tor Vergata".

Work Experience


Intern

Oct. 2021 - present

NEC Laboratories Europe

https://www.neclab.eu/


Student Researcher

Oct. 2017 - Dec. 2019

CNIT

Developer and maintainer for FlowBlaze and XTRA, open source projects for fast and stateful packet processing in hardware. Projects conducted under the H2020-5G PICTURE grant.

Developed a railway use-case scenario for ensuring session continuity as part of the H2020-5G PICTURE project.

https://www.cnit.it/


Academic Tutor

Oct. 2020 - March 2021

University of Rome "Tor Vergata"

Academic tutor for the Computer Fundamentals course

https://en.uniroma2.it/


Selected Publications

Metronome: adaptive and precise intermittent packet retrieval in DPDK

M. Faltelli, G. Belocchi, F. Quaglia, S. Pontarelli, G. Bianchi
ACM CoNEXT 2020
Acceptance Ratio: 23%
BibTex PDF Extension Video

XTRA: Towards Portable Transport Layer Functions

G. Bianchi, M. Welzl, A. Tulumello, F. Gringoli, G. Belocchi, M. Faltelli, and S. Pontarelli
IEEE Transactions on Network and Service Management
Acceptance Ratio: 15%
Impact Factor: 4.682
BibTex PDF

Offloading Online MapReduce tasks with Stateful Programmable Data Planes

V. Bruschi, M. Faltelli, A. Tulumello, S. Pontarelli, F. Quaglia, and G. Bianchi
1st Workshop on Flexible Network Data Plane Processing (NETPROC 2020)
BibTex PDF

Back to the Future: Towards Hardware ''Netputing'' Architectures

G. Bianchi, M. Faltelli and V. Bruschi
2020 Mediterranean Communication and Computer Networking Conference (MedComNet)
BibTex

A fully portable TCP implementation using XFSMs

G. Bianchi, M. Welzl, A. Tulumello, G. Belocchi, M. Faltelli, and S. Pontarelli
Proceedings of the ACM SIGCOMM 2018 Conference on Posters and Demos
BibTex PDF



Education


PhD in Computer Science

Nov. 2019 - Present

University of Rome "Tor Vergata"

Advisors: Prof. Giuseppe Bianchi, Prof. Francesco Quaglia

https://en.uniroma2.it/

Master's Degree in Computer Engineering

Oct. 2017 - Oct. 2019

University of Rome "Tor Vergata"

Thesis: A state-machine based platform for portable transport protocols

Final evaluation: 110/110 cum laude

Advisors: Prof. Giuseppe Bianchi, Prof. Francesco Quaglia

https://en.uniroma2.it/

Bachelor's Degree in Computer Engineering

Oct. 2014 - Oct. 2017

University of Rome "Tor Vergata"

Evaluation: 110/110

https://en.uniroma2.it/