Marco Faltelli

prof_pic.jpg

Room FF50049

Via Enrico Fermi 45

00044 Frascati, Italy

I am a Researcher in the ENEA High Performance Computing Lab.

In June 2023 I obtained my PhD in Computer Science under the supervision of Prof. Giuseppe Bianchi and Prof. Francesco Quaglia.
My research activities combine computer networking and computer architecture to design high performing, scalable architectures for both network hardware and software solutions.

My research has been awarded with a Microsoft Research PhD Fellowship. I’ve been a Research Intern at Microsoft Research Cambridge under the supervision of Sergey Legtchenko during Summer 2022 .

In the past, I collaborated with CNIT on the 5G-PICTURE European project.

I further collaborate with Axbryd, a startup company founded from the NetProg group of the University of Rome “Tor Vergata”.

I am always looking for collaboration and feedbacks, also from students. If your research interests are close to mine, feel free to reach out!

news

Mar 20, 2026 “Characterizing the Impact of Congestion in Modern HPC Interconnects” has been accepted to ISC High Performance 2026!
Feb 28, 2025 “FIPLib: An Image Processing Library for FPGAs Using High-Level Synthesis” has been accepted to the International Journal of Parallel Programming!
Feb 11, 2025 “Fast and Energy-Efficient N-Body Simulation on FPGA through High-Level Synthesis” has been accepted to PDP 2025!
Jan 17, 2025 New article posted! How To: NVIDIA Forward Compatibility between different CUDA and GPU Driver versions on Medium
Dec 16, 2024 “COREC: Concurrent Non-Blocking Single-Queue Receive Driver for Low Latency Networking” has been accepted to Elsevier Computer Networks!

selected publications

2026

  1. ISC 2026
    Characterizing the Impact of Congestion in Modern HPC Interconnects
    L. Piarulli, M. Faltelli, D. Pleiter, and 7 more authors
    2026

2025

  1. GARR 2025
    CLIC (Cloud In Cresco): towards HPC/HPDA-as-a-Service
    Marco Faltelli, Alessandro Peloso, Francesco Iannone, and 3 more authors
    In GARR Conference 2025, 2025
  2. IJPP
    FIPLib: An Image Processing Library for FPGAs Using High-Level Synthesis
    Paolo Palazzari, Marco Faltelli, and Francesco Iannone
    International Journal of Parallel Programming, 2025
  3. PDP 25
    Fast and Energy-Efficient N-Body Simulation on FPGA through High-Level Synthesis
    Paolo Palazzari, Marco Faltelli, Francesco Iannone, and 1 more author
    In 2025 33rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2025
  4. Elsevier CN
    COREC: Concurrent non-blocking single-queue receive driver for low latency networking
    Marco Faltelli, Giacomo Belocchi, Francesco Quaglia, and 1 more author
    Computer Networks, 2025

2023

  1. IEEE/ACM ToN
    Metronome: Adaptive and Precise Intermittent Packet Retrieval in DPDK (extended version)
    Marco Faltelli, Giacomo Belocchi, Francesco Quaglia, and 2 more authors
    IEEE/ACM Transactions on Networking, 2023
  2. PhD Thesis
    Towards resilient and effective Network Services
    Marco Faltelli
    PhD Thesis, 2023

2020

  1. ACM CoNEXT
    Metronome: Adaptive and Precise Intermittent Packet Retrieval in DPDK
    Marco Faltelli, Giacomo Belocchi, Francesco Quaglia, and 2 more authors
    In ACM CoNEXT, 2020
  2. IEEE ICIN
    Offloading Online MapReduce tasks with Stateful Programmable Data Planes
    Valerio Bruschi, Marco Faltelli, Angelo Tulumello, and 3 more authors
    In 2020 23rd Conference on Innovation in Clouds, Internet and Networks and Workshops (ICIN), 2020

2019

  1. IEEE TNSM
    XTRA: Towards Portable Transport Layer Functions
    Giuseppe Bianchi, Michael Welzl, Angelo Tulumello, and 4 more authors
    IEEE Transactions on Network and Service Management, 2019

2018

  1. ACM SIGCOMM
    A Fully Portable TCP Implementation Using XFSMs
    Giuseppe Bianchi, Michael Welzl, Angelo Tulumello, and 3 more authors
    In Proceedings of the ACM SIGCOMM 2018 Conference on Posters and Demos, 2018, 3rd place in Student Research Competition!